Think a skyscraper of data cells 64 cells high
Western Digital showcased initial capacities of the world’s first 64-layer 3D NAND technology back in July 2016. They have now announced that it has commenced pilot production of the company’s 512 Gigabit three-bits-per-cell (X3) 64-layer 3D NAND (BICS3) chip in Yokkaichi, Japan, with mass production expected in the second half of 2017.
The first ever 512Gb 64-layer 3D NAND flash chips are based on a vertical stacking technology that Western Digital and manufacturing partner Toshiba call BiCS (Bit Cost Scaling), which stores three bits of data per cell and stacks those cells 64 layers high. Three-dimensional NAND overrides physical limitations of NAND flash, which are restricted by 10 nanometers transistor sizes.
“The launch of the industry’s first 512Gb 64-layer 3D NAND chip is another important stride forward in the advancement of our 3D NAND technology, doubling the density from when we introduced the world’s first 64-layer architecture in July 2016,” said Dr. Siva Sivaram, executive vice president, memory technology, Western Digital. “This is a great addition to our rapidly broadening 3D NAND technology portfolio. It positions us well to continue addressing the increasing demand for storage due to rapid data growth across a wide range of customer retail, mobile and data center applications.”
Western Digital is set to present a technical paper on high aspect ratio semiconductor processing advancements tomorrow at the International Solid State Circuits Conference (ISSCC).